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allwinner: power: add enable switches for DCDC1/5
author
Andre Przywara
<
[email protected]
>
Wed, 24 Oct 2018 15:38:12 +0000
(16:38 +0100)
committer
Andre Przywara
<
[email protected]
>
Wed, 14 Nov 2018 09:50:06 +0000
(09:50 +0000)
The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
isn't critical, since those rails are on by default (and are needed for
every board), but it is inconsistent.
Add the respective enable bits for those two rails.
Signed-off-by: Andre Przywara <
[email protected]
>
plat/allwinner/sun50i_a64/sunxi_power.c
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diff --git
a/plat/allwinner/sun50i_a64/sunxi_power.c
b/plat/allwinner/sun50i_a64/sunxi_power.c
index 8db248b428bf5b5af62dbf91af845b33a11de93c..bc796c5d64d5bd3f039066c3fbc336411edc0bc5 100644
(file)
--- a/
plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/
plat/allwinner/sun50i_a64/sunxi_power.c
@@
-181,8
+181,8
@@
struct axp_regulator {
unsigned char switch_reg;
unsigned char switch_bit;
} regulators[] = {
- {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x
ff, 9
},
- {"dcdc5", 800, 1840, 10, 32, 0x24, 0x
ff, 9
},
+ {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x
10, 0
},
+ {"dcdc5", 800, 1840, 10, 32, 0x24, 0x
10, 4
},
{"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3},
{"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4},
{"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5},